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# Created by write_sdc on Mon Jun 17 07:32:04 2019

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set sdc_version 2.0

set_units -time ns
create_clock [get_ports clk_i]  -name core_clock  -period 5.6  -waveform {0 2.8}
set_input_delay -clock core_clock  0  [get_ports clk_i]
set_input_delay -clock core_clock  0  [get_ports rst_ni]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[63]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[62]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[61]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[60]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[59]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[58]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[57]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[56]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[55]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[54]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[53]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[52]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[51]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[50]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[49]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[48]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[47]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[46]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[45]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[44]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[43]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[42]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[41]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[40]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[39]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[38]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[37]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[36]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[35]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[34]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[33]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[32]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[31]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[30]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[29]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[28]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[27]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[26]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[25]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[24]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[23]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[22]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[21]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[20]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[19]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[18]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[17]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[16]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[15]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[14]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[13]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[12]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[11]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[10]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[9]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[8]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[7]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[6]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[5]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[4]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[3]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[2]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[1]}]
set_input_delay -clock core_clock  0  [get_ports {boot_addr_i[0]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[63]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[62]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[61]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[60]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[59]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[58]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[57]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[56]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[55]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[54]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[53]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[52]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[51]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[50]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[49]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[48]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[47]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[46]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[45]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[44]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[43]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[42]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[41]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[40]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[39]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[38]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[37]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[36]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[35]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[34]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[33]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[32]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[31]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[30]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[29]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[28]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[27]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[26]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[25]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[24]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[23]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[22]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[21]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[20]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[19]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[18]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[17]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[16]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[15]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[14]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[13]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[12]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[11]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[10]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[9]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[8]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[7]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[6]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[5]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[4]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[3]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[2]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[1]}]
set_input_delay -clock core_clock  0  [get_ports {hart_id_i[0]}]
set_input_delay -clock core_clock  0  [get_ports {irq_i[1]}]
set_input_delay -clock core_clock  0  [get_ports {irq_i[0]}]
set_input_delay -clock core_clock  0  [get_ports ipi_i]
set_input_delay -clock core_clock  0  [get_ports time_irq_i]
set_input_delay -clock core_clock  0  [get_ports debug_req_i]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[aw_ready]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[ar_ready]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[w_ready]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b_valid]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][id][3]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][id][2]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][id][1]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][id][0]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][resp][1]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[b][resp][0]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r_valid]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][id][3]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][id][2]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][id][1]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][id][0]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][63]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][62]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][61]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][60]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][59]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][58]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][57]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][56]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][55]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][54]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][53]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][52]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][51]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][50]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][49]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][48]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][47]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][46]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][45]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][44]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][43]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][42]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][41]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][40]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][39]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][38]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][37]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][36]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][35]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][34]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][33]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][32]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][31]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][30]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][29]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][28]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][27]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][26]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][25]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][24]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][23]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][22]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][21]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][20]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][19]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][18]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][17]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][16]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][15]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][14]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][13]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][12]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][11]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][10]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][9]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][8]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][7]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][6]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][5]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][4]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][3]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][2]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][1]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][data][0]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][resp][1]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][resp][0]}]
set_input_delay -clock core_clock  0  [get_ports {axi_resp_i[r][last]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][id][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][id][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][id][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][id][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][63]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][62]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][61]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][60]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][59]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][58]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][57]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][56]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][55]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][54]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][53]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][52]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][51]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][50]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][49]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][48]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][47]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][46]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][45]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][44]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][43]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][42]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][41]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][40]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][39]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][38]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][37]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][36]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][35]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][34]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][33]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][32]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][31]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][30]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][29]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][28]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][27]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][26]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][25]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][24]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][23]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][22]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][21]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][20]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][19]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][18]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][17]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][16]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][15]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][14]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][13]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][12]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][11]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][10]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][9]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][8]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][addr][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][len][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][size][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][size][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][size][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][burst][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][burst][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][lock]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][cache][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][cache][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][cache][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][cache][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][prot][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][prot][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][prot][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][qos][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][qos][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][qos][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][qos][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][region][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][region][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][region][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][region][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw][atop][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[aw_valid]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][63]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][62]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][61]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][60]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][59]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][58]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][57]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][56]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][55]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][54]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][53]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][52]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][51]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][50]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][49]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][48]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][47]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][46]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][45]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][44]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][43]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][42]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][41]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][40]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][39]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][38]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][37]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][36]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][35]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][34]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][33]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][32]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][31]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][30]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][29]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][28]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][27]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][26]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][25]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][24]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][23]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][22]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][21]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][20]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][19]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][18]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][17]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][16]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][15]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][14]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][13]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][12]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][11]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][10]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][9]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][8]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][data][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][strb][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w][last]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[w_valid]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[b_ready]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][id][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][id][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][id][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][id][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][63]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][62]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][61]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][60]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][59]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][58]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][57]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][56]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][55]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][54]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][53]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][52]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][51]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][50]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][49]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][48]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][47]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][46]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][45]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][44]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][43]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][42]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][41]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][40]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][39]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][38]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][37]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][36]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][35]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][34]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][33]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][32]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][31]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][30]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][29]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][28]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][27]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][26]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][25]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][24]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][23]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][22]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][21]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][20]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][19]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][18]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][17]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][16]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][15]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][14]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][13]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][12]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][11]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][10]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][9]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][8]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][addr][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][7]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][6]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][5]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][4]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][len][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][size][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][size][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][size][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][burst][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][burst][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][lock]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][cache][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][cache][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][cache][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][cache][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][prot][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][prot][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][prot][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][qos][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][qos][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][qos][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][qos][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][region][3]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][region][2]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][region][1]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar][region][0]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[ar_valid]}]
set_output_delay -clock core_clock  0  [get_ports {axi_req_o[r_ready]}]
